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Power-saving flip flop invented

An innovative way to reduce power consumption

Japanese technology firm Toshiba has found an innovative way to reduce power consumption in mobile devices.

The company announced it has developed a flip-flop circuit based on a 40nm CMOS process that dissipates 77% less power than a standard flip-flop.

Tests have further shown that the latest invention can achieve a 24% reduction in total power consumption when applied to a wireless LAN chip.

Flip-flop circuits are essential for the functioning of digital devices like computers and mobile phones.

A typical system-on-a-chip (SoC) present in digital equipment requires 100,000 to 10 million flip-flops for its operation.

However, flip-flop circuits make use of clock buffers that lead to a large amount of power consumption.

Toshiba got away with the clock buffer in the new flip-flop, while still getting it to work optimally.

Previously, clock gating has been used by manufacturers to reduce power consumption in digital equipment, but it was not found to be very effective.

Copyright Press Association 2011

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